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mds 1532 g 1 revision 060804 www.idt.com 110 mh z t riple 8- bit adc with c lock g enerator ICS1532 features ? triple 8-bit analog-to-digital conversion ? 10 to 110 mhz operation ? direct connection to analog input data ? internal ac coupling capacitors ? internal camp circuit and external clamp inputs ? optional external phase detector enable input ? coast ? uses 3.3 and 2.5 vdc ? 5 v tolerant digital inputs ? integrated amplifier with ad justable gain and offset ? dynamic phase adjust (dpa) ? software adjustable analog sample point ? low jitter ? two additional plls ? programmable spread spectrum ? automatic power-on reset detection ? standard i 2 c 2-wire serial interface ? two address sets available via external pin ? lock detection in both hardware and software ? 144-pin low-profile quad flat pack (lqfp) package general description the ICS1532 is a high-per formance, cost-effective, 3-channel, 8-bit analog-to-digital converter with an integrated line-locked clock generator. they are part of a family of chips fo r high-resolution video applications that use analog inputs, such as lcd monitors, projectors, plasma displays, and hdtvs. using low-voltage cmos mixed-signal technology, they are an effective data-capture solution for vga to uxga. the ICS1532 chips offer analog-to-digital data conversion and synchronized pixel-clock generation up to 110 mega samples per second, (msps) or 110 mhz. the dynamic phase adjust (dpa) circuitry allows end-user control over the pixel clock phase, relative to the recovered sync signal and analog pixel data. the ICS1532 provides two 24-bit pixels per clock. an adcsync output pin provides recovered hsync in phase with the adcrclk output to be used to synchronize horizontal timing. a clamp signal can be generated internally or provided through the clamp pin. an adjustable-gain video amplifier fine tunes the analog signal. the pll uses an internal programmable feedback divider. two additional, independent programmable plls, each with spread-spectrum functionality, can support memory and panel clock requirements. block diagram clamp adc clamp adc clamp adc dpa pll red green blue coast hsync ra0-ra7 rb0-rb7 ga0-ga7 gb0-gb7 ba0-ba7 bb0-bb7 adcsync adcrclk ref serial if xtal osc sda scl por pll spread spectrum pll spread spectrum mclk pclk xtal in xtal out
110 mh z t riple 8- bit adc with c lock g enerator ICS1532 mds 1532 g 2 revision 060804 www.idt.com table of contents section title page chapter 1 summary ............................................................................................................... ..............3 chapter 2 pin diagram and listings.............................................................................................. .....5 chapter 3 functional blocks ..................................................................................................... ..........8 chapter 4 register set .......................................................................................................... .............11 chapter 5 dpa operation......................................................................................................... ..........18 chapter 6 osc divider & oscout.................................................................................................. .19 chapter 7 loop filter........................................................................................................... ...............19 chapter 8 pll parameter settings ................................................................................................ ...19 chapter 9 input termination................ ............... ......................... ................. .............. .............. .........20 chapter 10 programming.......................................................................................................... .........21 chapter 11 ac/dc operating condi tions................ ................. .................. ............. .............. ...........25 chapter 12 timing diagrams...................................................................................................... .......30 chapter 13 package dimensions................................................................................................... ...35 chapter 14 ordering information................................................................................................. .....37
110 mh z t riple 8- bit adc with c lock g enerator mds 1532 g 3 revision 060804 www.idt.com ICS1532 chapter 1 summary the ICS1532 is the ideal device for capturing analog rgb from a personal computer or other sources into the digital domain for display on a digital device such as an lcd panel. contained inside the ICS1532 device are the following blocks to accomplish this: ? main pll - re-generates required clock for sampling analog input data ? dpa - adjusts the phase of the sampling clock. ? clamps - controls the adc?s zero code value. ? amplifiers - controls the adc?s full scale code value. ? adc - three adcs converts the analog input into digital. ? i2c - standard i 2 c bus used for controlling the device ? por - power on reset for the i2c interface ? two spread spectrum utility plls - for generating any other clocks needed by the system. 1.1 main phase-locked loop (pll) main pll - the main pll is used for re-generating the clocks needed to properly sample the incoming analog signals. figure 1-1 simplified pll diagram the heart of the ICS1532 is a voltage controlled oscillator (vco). the vco?s speed is controlled by the voltage on the loop filter. this voltage will be described later in this section. 1.2 vco divider (vcod) the vco?s clock output is first passed through the vco divider (vcod). the vcod allows the vco to operate at higher speeds than the required output clock. note : under normal, locked operation the vcos has no effect on the speed of the output clocks, just the vco frequency. 1.3 dynamic phase adjust (dpa) the output of the vcos is then sent through the dynamic phase adjust (dpa) for phase adjustment and also the 12 bit internal feedback divider. the feedback divider controls how many clocks are seen during every cycle of the input reference. 1.4 feedback divider (fbd) the feedback divider output is a 4 clk wide signal called adcsync. the adcsync signal is aligned with the output clocks and is intended to be used by the system as a replacement for the hsync input, which is of indeterminate qua lity and is not aligned with the output clocks. 1.5 phase frequency detector (pfd) the phase frequency detector (pfd) then compares adcsync to the selected input hsync and controls the filter voltage by enabling and disabling the charge pump. the charge pump has programmable current drive and will source and sink current as ap propriate to keep the input hsync and the adcsync output aligned. the pfd?s hsync input is conditioned by a high-performance schmitt trigger. this preconditioned hsync signal, called ref, is provided as a clean reference signal with a short transition time can be output on pin 112. 1.6 osc input the high-frequency osc input pin, has a 7-bit user programmable divider can also be selected as the loop input. this selection allows the loop to operate from
110 mh z t riple 8- bit adc with c lock g enerator ICS1532 mds 1532 g 4 revision 060804 www.idt.com any appropriate, single ended source, typically a crystal oscillator. either the conditioned hsync input or the loop output (recovered hsync) is available at the func pin, and is aligned with the output clocks. 1.7 dynamic phase adjust - dpa the dpa is used for adjusting the phase relationship of the main pll?s re-generated clock to the incoming analog data to assure properly sampled analog data. the dynamic phase adjust (dpa) allows a programmable clock delay relative to the input hsync signal. a delay of up to one clock period is programmable: see chapter 5, ?dpa operation? for more details. 1.8 clamps the ICS1532 contains clamping circuitry to compensate for non zero volt black levels on the incoming video lines. clamping causes the device to charge internal level shif ting capacitors to the complementary voltage level of the analog input. this guarantees that the input is in the proper voltage range to be converted by the adc and also has the effect of making whatever the analog voltage level on the inputs is during the clamp interval, equal to approximately a 00 code. clamping may be in itiated either internally, by the adcsync signal, or externally via the active high clamp input pin. typically, clamping occurs just after the hsync signal goes active. however, with the externally input clamp signal, any area where the incoming video is at the black level may be used. 1.9 analog amplifiers the ICS1532 contains three independently controlled analog amplifiers that prepare the incoming analog inputs to be converted by the adc. these amplifiers have programmable gain and are to be adjusted by the system so that the analog output code range is as wide as practically possible. 1.10 digital to analog converters the clamped output of the ICS1532?s analog amplifiers is sent to the adc?s to convert the analog input?s into digital equivalents. 1.11 i 2 c bus serial interface the ICS1532 uses a 5 volt tolerant, industry-standard i 2 c-bus serial interface that runs at either low speed (100 khz) or high speed (400 khz). the interface uses 4 banks of indexed register s: there are write-only, read/write, and read-only registers. two ICS1532 devices can be addressed, according to the state of the i2cadr pin. when this pin is low, the read address is 49h, and the write address is 48h. when the pin is high, the read address is 4bh, and the write address is 4ah. see chapter 10, ?programming? 1.12 digital inputs all of the ICS1532?s digital inputs are 5 v-tolerant. 1.13 digital data outputs the ICS1532 uses slew c ontrolled cmos outputs and are designed to be connected directly to the scaler or data transmitter inputs with no series resistors. 1.14 automatic power-on reset detection the ICS1532 has automatic power-on reset detection (por) circuitry and it resets itself if the supply voltage drops below ~1.8 vdc. no external connection to a reset signal is required and it may be, but a active low reset# input is also provid ed and may be held low for ~10ms to reset the ICS1532. 1.15 two spread spectrum utility plls besides the main, pixel clock pll, the ICS1532 has two other independent plls for use as needed. typically, these plls are used to drive memory and panel data clocks. both of these additional plls are tailored for the required frequency ranges. each supports software-controlled spread-spectrum clock dithering to reduce measured electro-magnetic interference (emi). 1.16 programmable outputs for general-purpose outputs, the ICS1532 provides programmable pins psel3, psel2, and psel1 (reg 37:2-0).
110 mh z t riple 8- bit adc with c lock g enerator mds 1532 g 5 revision 060804 www.idt.com ICS1532 chapter 2 pin diagram and listings figure 2-1. pin diagram 7 2 v s s q a d c 7 1 g a 2 7 0 g a 3 6 9 g a 4 6 8 g a 5 6 7 g a 6 6 6 g a 7 6 5 v d d q a d c 6 4 v s s q a d c 6 3 g b 0 6 2 g b 1 6 1 g b 2 6 0 g b 3 5 9 g b 4 5 8 g b 5 5 7 v d d q a d c 5 6 v s s q a d c 5 5 a d c s y n c 5 4 a d c r c l k 5 3 v d d d a d c 5 2 v s s d a d c 5 1 g b 6 5 0 g b 7 4 9 b a 0 4 8 b a 1 4 7 b a 2 4 6 b a 3 4 5 v d d q a d c 4 4 v s s q a d c 4 3 b a 4 4 2 b a 5 4 1 b a 6 4 0 b a 7 3 9 b b 0 3 8 b b 1 3 7 v d d q a d c ( 2 . 5 ) ( 2 . 5 ) 108 vddxtl 107 xout 106 xin 105 vssxtl 104 pnlclk 103 vddpclk 102 vsspclk 101 mclk 100 vddmclk 99 vssmclk 98 reserved 97 reserved 96 vssqadc 95 ra0 94 ra1 93 ra2 92 ra3 91 ra4 90 ra5 89 vddqadc 88 vssqadc 87 ra6 86 ra7 85 rb0 84 rb1 83 rb2 82 rb3 81 vddqadc 80 vssqadc 79 rb4 78 rb5 77 rb6 76 rb7 75 ga0 74 ga1 73 vddqadc v d d q 1 0 9 1 1 0 1 1 1 r e f 1 1 2 1 1 3 r e s e r v e d n c n c n c n c n c n c n c n c n c n c n c n c n c n c v s s q s t a t u s # o s c o u t c l k 1 1 4 v s s s u b 1 1 6 n c 1 1 7 n c 1 1 8 n c 1 1 9 1 2 4 v d d a 1 3 4 v s s a 1 3 5 n c 1 3 6 s c l 1 3 7 s d a 1 3 8 v s s d 1 3 9 v d d d 1 4 0 p d e n 1 4 1 s b a d r 1 4 2 x f i l r e t 1 4 3 e x t f i l 1 4 4 1 1 5 1 2 0 1 2 1 1 2 2 1 2 3 1 2 5 1 2 6 1 2 7 1 2 8 1 2 9 1 3 0 1 3 1 1 3 2 1 3 3 vss 1 reset 2 vssdadc (2.5) 3 vss 5 hsync 6 vsssub 7 psel3 ablue 15 r 16 avss 18 avss 21 vssaadc 25 vssaadc 26 vddaadc 27 clamp 28 vddqadc 29 bb7 30 bb6 31 bb5 32 bb4 33 bb3 34 bb2 35 vssqadc 36 4 13 vdddadc (2.5) psel1 8 psel2 9 10 nc 11 vss(test2) 12 vss(test1) avss 14 ablue_ nc 17 agreen 19 agreen_r 20 ared 22 ared_r 23 vddaadc (2.5) 24 (2.5) (2.5) (2.5)
110 mh z t riple 8- bit adc with c lock g enerator ICS1532 mds 1532 g 6 revision 060804 www.idt.com 2.0.1 pin listing by functional grouping table 2-1. pin listing by functional group pin group pin name pin type pin description pin # clock in clamp input external clamp input - optional 28 clock in hsync input horizontal sync input 6 clock in xin input crystal input - connect 14.31818 mhz, 20pf, parallel resonance crystal or and external 14.31818-mhz clock source 106 clock out adcrclk output analog-to-digital conv erter reference clock ? half-rate pixel clock for latching digital output pixel data. 54 clock out adcsync output analog-to-digital converter sync ? recovered hsync output. latch with adcrclk. 55 clock out clk output full rate pixel clock to adc section ? normally not used. see adrcrclk 114 clock out mclk output memory clock - independent user-programmable clock source #1 101 clock out oscout output oscillator output - native oscillator or divided oscillator output 113 clock out pnlclk output panel clock - independent user-programmable clock source #2 104 clock out ref output reference - various reference line clock sync signals. 112 clock out xout output crystal output - connect to the crystal above or leave open 107 control in scl input serial clock for i 2 c - 5-v tolerant input clock from an i 2 c bus 137 control in sbadr input i 2 c serial bus address ? low, address is 49h for reads and 48h for writes ? high, address is 4bh for reads and 4ah for writes 142 control in reset input reset input - optional ? low - device held in reset state ? high - normal operation -pull high if unused 142 control i/o sda i/o serial data - 5-v tolerant pin data pin for an i 2 c bus 138 control out psel1 - 3 output programmable outputs see register 37h. 8, 9, 10 analog input blue, green, red input analog blue, green and red inputs ? accepts analog data for the adcs blue, green, and red converters 15, 19, 22 analog input ablue_r agreen_r ared_r input analog blue, green an d red signal returns ? these pins provide a return path for the analog input data 16, 20, 23 data output ba7 ? ba0, ga7 ? ga0, ra7 ? ra0 output blue ?a? 7?0, green ?a? 7?0, and red ?a? 7?0. ? output first blue, green, and red digital pixel data, respectively. ? a7 = msb see figure 2-1 data output bb7 ? bb0, gb7 ? gb0, rb7 ? rb0 output blue ?b? 7?0, green ?b? 7?0, and red ?b? 7?0. ? outputs second blue, green, and red digital pixel data, respectively. ? a7 = msb see figure 2-1 clock in extfil input external filter- optional external filter in put between self and xfilret 144 clock in pden/coast input +5 phase-detector enable - can disable the charge pump with reg 0:1-0 141
110 mh z t riple 8- bit adc with c lock g enerator mds 1532 g 7 revision 060804 www.idt.com ICS1532 clock in status# output status - active-low when locked pin works with reg 2c:1-0 111 clock in xfilret input external filter return. - external filter input between self and extfil 143 ground avss ground main analog ground - connect to the common ground plane 14, 18, 21 ground vss ground main pll ground - connect to the common ground plane 1 & 5 ground vssa ground main pll analog ground - connect to the common ground plane 135 ground vssaadc(2.5) ground analog adc ground - ground for 2.5 volt analog portions of the adc ? connect to the common ground plane 25 & 26 ground vssd ground digital ground - connect to the common ground plane 139 ground vssdadc(2.5) ground digital adc ground - ground for 2.5 volt digital portions of the adc ? connect to the common ground plane 3, 52 ground vssmclk ground mclk pll ground - connect to the common ground plane 99 ground vsspclk ground pnlclk pll ground - connect to the common ground plane 102 ground vssq ground main pll output ground - connect to the common ground plane 110 ground vssqadc ground pixel data output driver ground ? connect to the common ground plane 36, 44, 56, 64, 72, 80, 88, 96 ground vsssub ground ground for substrate - connect to the common ground plane 7, 116 ground vsstest2 vsstest1 ground ground or test outputs - connect to the common ground plane 12, 13 ground vssxtl ground crystal oscillator ground - connect to the common ground plane 105 power vdda 3.3 (3.3 v) supply for analog pixel pll circuitry 134 power vddaadc(2.5) 2.5 (2.5 v) supply for analog adc circuitry 24 & 27 power vddd 3.3 (3.3 v) supply for main pll and i 2 c bus 140 power vdddadc(2.5) 2.5 (2.5 v) supply for digital adc circuitry 4, 53 power vddmclk 3.3 (3.3 v) supply for mclk 100 power vddpclk 3.3 (3.3 v) supply for pnlclk 103 power vddq 3.3 (3.3 v) supply for output drivers 109 power vddqadc 3.3 (3.3 v) supply for pixel data output drivers 29, 37, 45, 57, 65, 73, 81, 89 power vddxtl 3.3 (3.3v) supply for crystal oscillator 108 nc no connect nc no connect - do not connect these pins. 11, 17, 117 - 133, 136 reserved reserved res. reserved - do not connect these pins. 97, 98 table 2-1. pin listing by functional group ( continued ) pin group pin name pin type pin description pin #
110 mh z t riple 8- bit adc with c lock g enerator ICS1532 mds 1532 g 8 revision 060804 www.idt.com chapter 3 functional blocks figure 3-1. pixel pll block diagram charge pump phase freq detector vco post- scaler divider ref_pol reg 0:2 feedback divider dynamic phase adjust extfil (144) xfilret (143) lock logic int filter filter select dpa_lock reg 12:0 pfd2-0 reg 1:2-0 pixel pll_lock reg 12:1 ps d re g 1:5-4 fil_sel reg 8:0 dpa_ os5-0 reg 4:5-0 fd bk7-0 reg 2:7-0 fdbk11-8 reg 3:3-0 reg 0:3 dpa_res1-0 reg 5:1-0 hsync (6) hsync_sel reg 0:7-6 mux in_sel reg 0:5 0 1 osc_div div 2 osc osc_div reg 7:7-0 oe_osc reg 2c:6 oscout (113) mux 0 1 2 3 osc_sel reg 2c:5-4 fdbkdivload reg 0:4 res_sel reg 8:6-4 shunt_sel reg 8:7 adc_func cap_sel reg 8:3-1 status (111) ref (112) ref mux reg 2c:2 0 1 fdbk_pol mux 1 0 reg 6:3 oe_tck reg 6:6 adc_clk clk (114) chip major/ minor rev reg 11:7-0 por static regs chip_ver reg 10:7-0 pixel pll reset reg a:7-4 dpa reset reg a:3-0 scl (137) sda (138) sbadr (142) 2-wire serial interface func normal func earl y func mux 0 1 early_fun c_sel reg 6:4 full-rate clock cp_en reg 0:0 coast (141) cp_pol reg 0:1 lcksel reg 2c:1-0 pnlclk_lock reg 12:2 mclk_lock reg 12:3
110 mh z t riple 8- bit adc with c lock g enerator mds 1532 g 9 revision 060804 www.idt.com ICS1532 figure 3-2. clk block diagram phase freq detector mux feedback divider reference divider pnlclk_pfd reg 24:4-2 pnlclk-m reg 20:7-0 pnlclk-n reg 21:7-0 divide by 2 pnlclk_lock reg 12:2 pnlclk (104) pnlclk_osd reg 24:1-0 pnlclk_oe reg 25:0 phase freq detector vco output scaler divider feedback divider mclk (101) mclk_pfd reg 2a:4-2 mclk-m reg 26:7-0 mclk_osd reg 2a:1-0 mclk-n reg 27:7-0 mclk_oe reg 2b:0 divide by 2 mclk_lock reg 12:3 reference divider crystal osc 14.318 mhz xin (106) 1 0 clk_sel reg 25:2 divide by 16 adc_clk osc vco spread spectrum output scaler divider pnlclk_ss reg 24:7-6 pnlclk_ssenb reg 25:1 pnlclk-ss1 reg 23:3-0 pnlclk-ss0 reg 22:7-0 xout (107) mclk_ss reg 2a:7-6 mclk-ss1 reg 29:3-0 mclk-ss0 reg 28:7-0 mclk_ssenb reg 2b:1 divide by 144 spread spectrum charge pump charge pump
110 mh z t riple 8- bit adc with c lock g enerator ICS1532 mds 1532 g 10 revision 060804 www.idt.com figure 3-3. adc block diagram b b 0 - b b 7 ( 3 9 , 3 8 , 3 5 , 3 4 , 3 3 , 3 2 , 3 1 , 3 0 ) a d c _ o e r e g 3 0 : 7 a d c _ i n v r e g 3 0 : 5 b a 0 - b a 7 ( 4 9 , 4 8 , 4 7 , 4 6 , 4 3 , 4 2 , 4 1 , 4 0 ) a d c _ o e r e g 3 0 : 7 a d c _ i n v r e g 3 0 : 5 g b 0 - g b 7 ( 6 3 , 6 2 , 6 1 , 6 0 , 5 9 , 5 8 , 5 1 , 5 0 ) a d c _ o e r e g 3 0 : 7 a d c _ i n v r e g 3 0 : 5 g a 0 - g a 7 ( 7 5 , 7 4 , 7 1 , 7 0 , 6 9 , 6 8 , 6 7 , 6 6 ) a d c _ o e r e g 3 0 : 7 a d c _ i n v r e g 3 0 : 5 r b 0 - r b 7 ( 8 5 , 8 4 , 8 3 , 8 2 , 7 9 , 7 8 , 7 7 , 7 6 ) a d c _ o e r e g 3 0 : 7 a d c _ i n v r e g 3 0 : 5 r a 0 - r a 7 ( 9 5 , 9 4 , 9 3 , 9 2 , 9 1 , 9 0 , 8 7 , 8 6 ) a d c _ o e r e g 3 0 : 7 a d c _ i n v r e g 3 0 : 5 s e t _ a d c r e g 3 0 : 4 8 8 8 8 8 r e d a d c b l o c k g r e e n a d c b l o c k b l u e a d c b l o c k 1 0 m u x o e _ a d c r c l k r e g 6 : 5 1 o e _ a d c s y n c r e g 6 : 4 0 m u x o e _ a d c s y n c r e g 6 : 4 a d c r c l k ( 5 4 ) i n p u t f u n c f u l l - r a t e c l o c k a d c s y n c ( 5 5 ) a b l u e ( 1 5 ) a b l u e _ r ( 1 6 ) a g r n ( 1 9 ) a g r n _ r ( 2 0 ) a r e d ( 2 2 ) a r e d _ r ( 2 3 ) c l a m p a n d a m p r e f e r e n c e v o l t a g e s c l a m p a n d a m p c l a m p a n d a m p a d c _ c l k a d c _ f u n c o e _ a d c r c l k r e g 6 : 5 a d c r c l k _ i n v r e g 3 0 : 2 1 0 m u x c l a m p _ s e l r e g 3 0 : 2 c l a m p ( 2 8 ) c l a m p _ p o l r e g 3 0 : 3 8 e a r l y _ f u n c _ s e l r e g 6 : 4 m u x d i v i d e b y 2 h a l f - r a t e c l o c k m u x f u n c _ d e l a y r e g 6 : 2 0 1 f u n c
110 mh z t riple 8- bit adc with c lock g enerator mds 1532 g 11 revision 060804 www.idt.com ICS1532 chapter 4 register set the tables in this chapter detail the functionality of the ICS1532 register set bits. the tables include the register locations, the bit positions , names, and definitions, along with th eir read/write access, reset values, and any special functions or capabilities. 4.1 reserved bits the ICS1532 has a number of reserved bits throughout th e register set. these bits provide enhanced test functions (intended for use only by ics manufactur ing) and calibration functions (intended for use in production environments). important: the customer must not change the value of rese rved bits. if the customer changes the default values of these reserved bits, normal operation of the ICS1532 can be affected. 4.2 register set conventions register set conventions include the following: ? an ?#? on the end if a register bit or pin name indicates active low. (low = true, high = false) ? bits are listed in the order of most-signifi cant bit (msb) to least-significant bit (lsb). ? unless otherwise indicated, bit se ttings are listed in terms of digital (and not hexadecimal) values. ? when a bit definition includes word(s ) in parentheses, the word in parent hesis is not part of the bit name, but is given to explain the origin of the bit?s name. 4.3 register set abbreviations and acronyms table 4-1 lists and defines abbreviations and acrony ms used specifically in this chapter. table 4-1. register set abbreviations and acronyms abbreviation or acronym definition d-dpa double-buffered / dynamic phase adjust. indicates double-buffered registers for which working registers load during a software dynamic phase adjust reset. (rega = xah ) d-mk double-buffered / memory clock. indicates double-buffered registers for which working registers load during a software mclk reset. (reg2d = 5xh) d-pk double-buffered / panel clock. indicates double-buffered registers for which working registers load during a software pnlclk reset. (reg2d = xah) d-pll double-buffered / phase-locked loop. indicates double-buffered registers for which working registers load during a software pixel pll reset. (rega = 5xh) in-a increment all. indicates a value that increments with each all-layer revision of the ICS1532. reg register r/w read/write
110 mh z t riple 8- bit adc with c lock g enerator ICS1532 mds 1532 g 12 revision 060804 www.idt.com 4.4 complete register set table 4-2. new register set outline register index register name register access bit # bit name brief description reset value 00h input control r/w 7-6 hsync_sel select hsync input threshold for main pll 0 ? see chapter 11-3, ?pin specific i/o ac parameters? 5 in_sel select main pll phase detector input ? 0 = hsync source selected by reg0:7-6 ? 1 = input is the osc pin 1 4 fdbk div load select load for feedback divider ? 0 = new values loaded on a pixel pll reset.-(normal operation) ? 1 = new values loaded on the hsync without a pll reset - only usable for small changes 0 3 fdbk_pol select feedback polarity for phase/frequency detector ? 0 = main/pixel pll uses the rising edge ? 1 = main/pixel pll uses the falling edge 0 2 ref_pol select polarity of external reference ? 0 = rising hsync edge selected ? 1 = falling hsync edge selected 0 1 cp_pol select polarity of coast input if reg0:0=1 ? 0 = charge pump enabled if coast pin high ? 1 = charge pump enabled if coast pin low 0 0 cp_en charge pump (cp) enable ? 0 = cp enabled by reg0:1 and coast ? 1 = cp always enabled - normal operation 1 01h loop control r/w. d-pll. 7-6 reserved reserved 0 5-4 vcos select vco scaler value vco frequency = (output frequency) * vcos(d) ? 00 = 2:1 ? 01 = 4:1 ? 10 = 8:1 ? 11 = 16:1 0 3 reserved reserved 0 2-0 icp icp - charge pump current ? 000 = ~2 a ? 001 = ~4 a ? 010 = ~8 a (typical with internal filter) ? 011 = ~16 a. ? 100 = ~32 a ? 101 = ~64 a ? 110 = ~120 a. ? 111 = ~190 a 0 02h fdbk div 0 r/w. d-pll. 7-0 fdbk [7-0] feedback divider lsb?s bits 7-0 - see reg3 for msb?s ? controls the number of clk outputs per hsync ? actual # of clk?s = 8 + (reg3 + reg2)d n/a 03h fdbk div 1 r/w. d-pll. 7-4 reserved reserved ? 3-0 fdbk [11-8] feedback divider msb?s bits 11-8 - see reg2 n/a 04h dpa offset r/w 7-6 reserved reserved 0 5-0 dpa_os dynamic phase adjust (dpa) offset ? see chapter 5, ?dpa operation? the value programmed here must be less than the dpa resolution controlled by reg5:1-0 0
110 mh z t riple 8- bit adc with c lock g enerator mds 1532 g 13 revision 060804 www.idt.com ICS1532 05h dpa control r/w. d-dpa. 7-2 reserved reserved ? 1-0 dpa_res dpa resolution (number of available delay elements) see chapter 5, ?dpa operation? ? 00 = 16 elements - supports 55 to 110 mhz ? 01 = 32 elements - supports 27 to 110 mhz ? 10 = reserved ? 11 = 64 elements - supports 14 to 64 mhz n/a 06h output enables r/w 7 reserved reserved 0 6 oe_tclk enable clk output to adc and clk pin 1 = must be enabled for normal operation 0 5 oe_adcrclk enable adcrclk clock output 0 4 oe_adcsync enable output for adcsync 0 3 func_sel select signal source for adc_func signal 0 = output of the feedback divider - normal operation 1 = adc_func output is ref 0 2 func_delay additional one clk delay for adc_func signal 0 1 reserved reserved 0 0 reserved reserved 0 07h osc divider r/w 7-0 osc_div oscillator divider value 0 ? 00000000 = reserved. ? 00000001 = (osc / 2) ? 00000010 = (osc / 2) / 2 ? 00000011 = (osc / 2) / 3, and so forth. 08h internal filter r/w 7 shunt_sel select additional cp capacitor 1 values? 6-4 res_sel select additional rs resistance 7 values? 3-1 cap_sel select additional cs capacitance 7 0 fil_sel selects loop filter select 1 = internal (typical) 0=external 1 09h reserved n/a 0ah pixel pll/ dpa resets write 7-4 pixel pll reset writing 5xh re sets pixel pll and loads working regs 1h through 3h n/a 3-0 dpa reset writing xah resets dpa and loads working reg 5h n/a 0bh-0fh reserved n/a 10h chip ver read 7-0 chip ver read chip version 32 decimal (20h) as in 153 2 20 11h chip rev read. in-a. 7-4 chip major rev value increments with major chip revision. 01 table 4-2. new register set outline ( continued ) register index register name register access bit # bit name brief description reset value 1 2 3 osc period
110 mh z t riple 8- bit adc with c lock g enerator ICS1532 mds 1532 g 14 revision 060804 www.idt.com 3-0 chip minor rev value increments with minor chip revision. 00 12h rd_reg read 7-4 reserved reserved n/a 3 pll_lock pixel pll lock status - 1 = locked, 0 = unlocked n/a 2 mclk_lock memory mclk lock status - 1 = locked, 0 = unlocked n/a 1 pclk_lock panel pll lock status - 1 = locked, 0 = unlocked n/a 0 reserved reserved n/a 13h-1fh reserved n/a 20h pnlclk-m r/w. d-pk. 7-0 pnlclk_m select value for pnlclk m reference divider 0 21h pnlclk-n r/w. d-pk. 7-0 pnlclk_n select value for pnlclk n feedback divider f pnlclk = (osc x (n + 8) / (m+2) 0 22h pnlclk-ss0 r/w. d-pk. 7-0 pnlclk_ss0 value for pnlclk spread-spectrum counter lsb?s bits 7-0 - controls amount of frequency spread allowed values = (288 *n / m) + 8 0 23h pnlclk-ss1 r/w. d-pk. 7-4 reserved reserved 0 3-0 pnlclk_ss1 value for pnlclk spr ead-spectrum counter msbs bits 11-8 see reg22 0 24h pnlclk-ssoe r/w. d-pk. 7-6 pnlclk_ss select pnlclk spread-spectrum gain 0 ? 0 = the gain is 1 ? 1 = the gain is 2 ? 2 = the gain is 4 ? 3 = the gain is 8 5 reserved reserved 0 4-2 pnlclk_pfd pnlclk phase/frequency detector gain ? 000 = gain is 1 ? 001 = gain is 2 ? 010= gain is 4 ? 011 = gain is 8, and so forth... ? 111 = gain is 128 0 1-0 pnlclk_osd pnlclk output scaler divider ? 00 = divide by 1 ? 01 = divide by 2 ? 10= divide by 4 ? 11 = divide by 8 0 25h pnlclk-oe r/w 7-3 reserved reserved 11100 2 clk_sel select input for pnlclk pll ? 0 = pnlclk pll input is from the crystal input ? 1 = input is from adc_clk, divided by 16 0 1 pnlclk_ssenb enable pnlclk spread-spectrum 0 0 pnlclk_oe enable pnlclk output 0 26h mclk-m r/w. d-mk. 7-0 mclk_m value for mclk m feedback divider 0 27h mclk-n r/w. d-mk. 7-0 mclk_n value for mclk n (numerator) feedback divider f mclk = (osc x (n + 8)) / (m+2) 0 table 4-2. new register set outline ( continued ) register index register name register access bit # bit name brief description reset value
110 mh z t riple 8- bit adc with c lock g enerator mds 1532 g 15 revision 060804 www.idt.com ICS1532 28h mclk-ss0 r/w. d-mk. 7-0 mclk_ss0 select mclk spread-spectrum counter lsb?s bits 7-0 see reg29 - controls amount of frequency spread allowed values = (288 *n / m) + 8 0 29h mclk-ss1 r/w. d-mk. 7-4 reserved reserved 1010 3-0 mclk_ss1 select mclk spread-spectrum counter msbs bits 11-8 see reg28 0 2ah mclk-ssoe r/w. d-mk. 7-6 mclk_ss select mclk spread-spectrum gain 0 ? 00 = the gain is 1 ? 01 = the gain is 2 ? 10 = the gain is 4 ? 11 = the gain is 8 5 reserved reserved 0 4-2 mclk_pfd select mclk phase/frequency detector gain ? 000 = gain is 1 ? 001 = gain is 2 ? 010 = gain is 4 ? 011 = gain is 8 ? 100 = gain is 16, and so forth... 0 1-0 mclk_osd select value for mclk output scaler divider ? 00 = divide by 1 ? 01 = divide by 2 ? 10 = divide by 4 ? 11 = divide by 8 0 2bh mclk-oe r/w 7-2 reserved reserved 010000 1 mclk_ssenb enable mclk spread-spectrum (1 = enabled) 0 0 mclk_oe enable mclk output (1 = enabled) 0 2ch output mux r/w 7 high_drive# disable high drive for adc pixel data output pins 0 6 oe_osc enable oscout output pin (1 = enabled) 1 5-4 osc_sel select oscout output ? 00 = oscout source is osc. ? 01 = oscout source is oscdivider (reg7) ? 10 = oscout source is osc/2. ? 11 = reserved 0 3 reserved reserved 0 2 refsel select ref status 0 1-0 lcksel# select active low output for status (pin 111) low when selection below is properly locked, else high ? 00 = main pixel pll ? 01 = mclk: memory clock ? 10 = reserved ? 11 = pnlclk: panel clock 1 2dh pll reset write 7-4 mclk_reset writing 5xh resets mclk pll & loads regs 26h~2bh n/a 3-0 pnlclk_reset writing xah resets pnlclk pll & loads regs 20~25h n/a 2eh-2fh reserved n/a 30h adc ctrl r/w 7 adc_oe enable adc output (1 = enabled) 0 ?????? 6 adc_inv invert adcrclk signal (1=latch data on rising edge) 0 5 force_adc force adc outputs to state of reg30:3 1 table 4-2. new register set outline ( continued ) register index register name register access bit # bit name brief description reset value
110 mh z t riple 8- bit adc with c lock g enerator ICS1532 mds 1532 g 16 revision 060804 www.idt.com ?????? 4 adc_clock_d adc clock state delay (1 = ?????) 0 3 adc_inv invert adc outputs (1- white = ff, 0 - white = 00) 0 2 clamp_sel clamp select ? 00 = external clamp (pin 28) ? 10 = internal clamp (same as func) 0 1 reserved reserved 0 0 clamp_pol polarity of clamping control signal 0 = active high clamp (normal operation) 1 = active low clamp 0 31h r_control r/w 7 r_vin_range red input voltage range (0=700mv, 1=1v) 1 6 reserved reserved 0 ???? 5 r_clamp_t3 red clamp time constant (0= nom., 1=0.3 nom.) 0 ???? 4 r_clamp_type soft/xhard clamp function 1 ???? 3 r_clamp_t5 red clamp time constant (0= nom., 1=0.5 nom.) 0 2-1 reserved reserved 1 0 xpd_r# power down red channel (0=powered down) 1 32h g_control r/w 7 g_fixed_gain green gain adjust. (0=100%, 1=140%) 1 6 reserved reserved 0 ???? 5 g_clamp_t3 green clamp time constant (0= nominal, 1=0.3 nom.) 0 ???? 4 g_clamp_type green soft/xhard clamp function 1 ???? 3 g_clamp_t5 green clamp time constant (0= nominal,1=0.5 nom.) 0 2 reserved reserved 1 1 sog sync on green 0 0 xpd_g# power down green channel (0=powered down) 1 33h b_control r/w 7 b_fixed_gain blue gain adjust. (0=100%, 1=140%) 1 6 reserved reserved 0 ???? 5 b_clamp_t3 blue clamp time constant (0= nominal, 1=0.3 nom.) 0 ???? 4 b_clamp_type blue soft/xhard clamp function 1 ???? 3 b_clamp_t5 blue clamp time constant (0= nominal,1=0.5 nom.) 0 2-1 reserved reserved 0 0 xpd_b# power down blue channel (0=powered down) 1 34h r_gain r/w 7-3 r_pga_gain fine adjus t red channel adc ladder voltage 00100 2-0 r_adc_gain adjust video amp gain for red channel of adc 000 35h g_gain r/w 7-3 g_pga_gain fine adjus t green channel adc ladder voltage 00100 2-0 g_adc_gain adjust video amp gain for green channel of adc 000 36h b_gain r/w 7-3 b_pga_gain fine adjus t blue channel adc ladder voltage 00100 2-0 b_adc_gain adjust video amp gain for blue channel of adc 000 37h psel r/w 7-4 bg_cal band gap calibration (0=normal operation) 0 3 xbg_pd# band gap power down (0=powered down) 1 2 psel3 state of psel3 (pin 10) 0 1 psel2 state of psel2 (pin 9) 0 0 psel1 state of psel1 (pin 8) 0 38h r_offset 7-0 r_offset red channel offset (00=minimum offset) 80h 39h g_offset 7-0 g_offset green channel offset (00=minimum offset) 80h table 4-2. new register set outline ( continued ) register index register name register access bit # bit name brief description reset value
110 mh z t riple 8- bit adc with c lock g enerator mds 1532 g 17 revision 060804 www.idt.com ICS1532 3ah b_offset 7-0 b_offset blue channel offset (00=minimum offset) 07h 3bh ibias 7-6 ibias_buf adc buffer bias adjustment 10 5-4 ibias_va video amp bias adjustment 10 3-0 ibias_adc adc bias adjustment 1010 3ch test_mux 7-3 ctm channel test mux 1010 2-0 bgtm band gap test mux 1010 table 4-2. new register set outline ( continued ) register index register name register access bit # bit name brief description reset value
110 mh z t riple 8- bit adc with c lock g enerator ICS1532 mds 1532 g 18 revision 060804 www.idt.com chapter 5 dpa operation figure 5-1. dpa offset (as determined by regs 04 and 05) table 5-1. dpa control reg 05:1-0 1. number of delay element units (decimal) 2. reg 04:5-0 max. value (hex) 3. pixel clock range (mhz) bit 1 bit 0 0 0 16 0f 55 110 0 1 32 1f 27 110 1 0 reserved reserved 1 1 64 3f 14 64 hsync clk offset when dpa_os [5-0] = 0 . . . . . . one unit of dpa delay t low one clock period t high clk offset when dpa_os [5-0] = 1 clk offset when dpa_os [5-0] = 2 clk offset when dpa_os [5-0] = max t high t high t high fixed delay 2.5 ns 1 unit of dpa delay 2 units of dpa delay maximum units of dpa delay
110 mh z t riple 8- bit adc with c lock g enerator mds 1532 g 19 revision 060804 www.idt.com ICS1532 chapter 6 osc divider & oscout the ICS1532 accepts either a crystal across xin and xout or a single ended clock on the xin input (with xout left open). see ta b l e 11 - 4 for crystal requirements. this input (o sc) may be output to the oscout pin at the same input frequency, half the input frequency, or divided by >2. this translates to osc, osc/2 and the osc divider and is selected by register2c:5~4. the osc divider works as follows, the period of the osc input becomes the high time of the osc_out signal and the low time is controlled by register 7. table 6-1 osc divider functionality chapter 7 loop filter the ICS1532 contains an internal loop filter and also supports the use of an exter nal loop filter configured as in figure 7-1 . selection between these two filters is controlled by register 8:7. a 0 selects the external, a 1 selects the internal filter. figure 7-1 external loop filter while the internal loop f ilter works well for most applications, idt still reco mmends the implementation of an external filter network on all designs. implementing the external loop filter gives the system engineer flexibility to add exter nal filter functionality if without having to alter the pcb. chapter 8 pll parameter settings settings for all standard vesa video modes are pro- vided by idt as a starting point for the systems engi- neer. these files are in human readable text files (*.ics files) and come bundled within the ICS1532 register editor tool. this tool directly drives the ICS1532eb evaluation board and can be downloaded from www.idt.com. parameter value osc divider frequency (input osc frequency) * [(register 7: 6~0) + 2] osc high time input osc period osc low time [reg7 + 1] * input osc period minimum osc divider 3 (reg7:6~0 = 0000001) maximum osc divider 257 (reg7 = 1111 1111) reserved osc divider 0 (reg7 = 0000 0000)
110 mh z t riple 8- bit adc with c lock g enerator ICS1532 mds 1532 g 20 revision 060804 www.idt.com chapter 9 input termination the ICS1532 is a high speed analog to digital converter capable of operating at 110 msps. since vga/vesa video is comp rised of 700 mv vpp waveforms potentially toggling high speed, care needs to be taken to preserve the quality of these analog input signals from reflections and coupled noise all the way to the input pins of the ICS1532. the r, g and b video inputs and their dedicated return signals must be? ? routed as a clean, minimal length traces to minimize loading and pickup ? 75 ohm characteristic impedance to eliminate reflections ? appropriate signal pairs being located as close as possible to each other and far from noise sources ? properly terminated as shown in figure 9-1 with termination resistors placed as close to the ICS1532 as possible. figure 9-1. recommended termination
110 mh z t riple 8- bit adc with c lock g enerator mds 1532 g 21 revision 060804 www.idt.com ICS1532 chapter 10 programming 10.1 i2c serial bus: data format figure 10-1. ICS1532 data format for i2c serial bus note: in general, the: ? lower nibble of the i 2 c register automatically increments after ea ch successive data byte is written to or read from the ICS1532. ? upper nibble of the i 2 c register does not automatically incremen t, and the software must explicitly re-address the ICS1532. as a result, to write or read all the ICS1532 registers, the software: ? must not index 0 and then do 64 one-byte transactions. ? must break the transactions into at least four separate bus transactions: (1) 00 to 0f (2) 10 to 1f (3) 20 to 2f (4) 30 to 3f write procedure for single register msb lsb s010010xwa a a slave address regsiter index data read procedure for single register msb lsb msb lsb s010010xwa as010010xra a slave address regsiter index slave address data repeat sta rt no a cknow ledge write procedure for multiple registers (note 1) msb lsb s010010xwa a a a a slave address regsiter index data data read procedure for multiple registers (note 1) msb lsb msb lsb s010010xwa as010010xra a a slave address regsiter index slave address data data repeat sta rt no a cknow ledge legend all values are sent with the most-significant bit (msb) first and least-significant bit (lsb) last. r = read = 1 w = w rite = 0 s = start (sda goes low when scl was high, then scl goes low too) a = ack = acknowledge = 0 a = nak = no acknowlege = 1 x = bit value that equals logic state of sbadr pin. = (dashed line) multiple transactions bus master drives signal to ICS1532 ICS1532 (slave device) drives signal to bus master stop stop stop stop
110 mh z t riple 8- bit adc with c lock g enerator ICS1532 mds 1532 g 22 revision 060804 www.idt.com 10.2 programming flow for modi fying pll and dpa settings figure 10-2. ICS1532 flow for capture/input clock pll start scaler determines mode changing pll parameters? set input, pfd gain, post scaler and feedback divider regs 0~3 yes pll s/w reset rega=50h pll locked? adjust pfd gain and/or post scaler no set dpa resolution, reg5 and dpa offset, reg4 yes dpa s/w reset rega=0ah correct phase relationship? no adjust dpa offset reg4 done yes no
110 mh z t riple 8- bit adc with c lock g enerator mds 1532 g 23 revision 060804 www.idt.com ICS1532 10.2.1 programming flow for modifying settings for spread spectrum figure 10-3. ICS1532 flow for pnlclk a nd mclk pll spread-spectrum settings start mclk from spread.ini set... m, n, pfd gain and output scaler mclk regs 26, 27 &2a done changing pll frequency? yes pll software reset reg2d = 5xh no changing spread settings? yes from spread.ini set... spread counter and gain mclk regs 28, 29 & 2a no start pnlclk from spread.ini set... m, n, pfd gain and output scaler pnlclk regs 20, 21 & 24 done changing pll frequency? yes pll software reset reg2d = xah no changing spread settings? yes from spread.ini set... spread counter and gain pnlclk regs 22, 23 & 24 no
110 mh z t riple 8- bit adc with c lock g enerator ICS1532 mds 1532 g 24 revision 060804 www.idt.com 10.2.2 programming flow for calibrating figure 10-4. ICS1532 flow for adc calibration initialize 1532/3 to default values begin adc calibration red offset (reg 38) = 80h green offset (reg 39) = 80h blue offset (reg 3a) = 80h presume that a line/screen with at least one white and one black pixel min red output code > min? no increment red offset reg 38 min red output code < min? no decrement red offset reg 38 repeat for green and blue offset max red output code = ffh? no increment red gain reg34 max red output code < max? no decrement red gain reg34 end adc calibration now, any values over min or under max indicate an out of calibration condidion max code is normally ~fah to allow for out of calibration detection min code is normally ~05h to allow for out of calibration detection repeat for green and blue gain store values in appropriate location
110 mh z t riple 8- bit adc with c lock g enerator mds 1532 g 25 revision 060804 www.idt.com ICS1532 chapter 11 ac/dc operating conditions 11.1 absolute maximum ratings ta b l e 11 - 1 lists absolute maximum ratings for the ics153 2. stresses above these ratings can cause permanent damage to the ICS1532. these ratings, which are standard values for ics commercially rated parts, are stress ratings only. functional operation of the ICS1532 at these or an y other conditions above those indicated in the operational sections of the s pecifications is not implied. exposure to absolute maximum rating conditions for exten ded periods can affect product relia bility. electrical parameters are guaranteed only over the recommended operating temperature range. during normal operation, the supply voltages fo r the ICS1532 must remain within the recommended operating conditions. note: electrostatic-sensitive device. do not open or handle except in a static-free workstation.) 11.2 recommended operating conditions table 11-1. ICS1532 absolute maximum ratings item rating notes vdd, vddq (see note) 4.3 v measured with respect to vss vddxadc (see note) 3.6 v m easured with respect to vss digital inputs vss -0.3 v to +5.5 v digital outputs vssq -0.3 v to vddq +0.3 v analog inputs vss -0.3 v to +5.5 v analog outputs vssa -0.3 v to vdda +0.3 v storage temperature -65 to +150 c junction temperature 125 c soldering temperature 260 c 20 seconds max table 11-2. environmental conditions parameter minimum typical maximum units ambient operating temperature 0 +70 c 3.3 power supply voltage +3.15 +3.3 +3.45 v 2.5 volt power supply voltage +2.35 +2.5 +2.65 v
110 mh z t riple 8- bit adc with c lock g enerator ICS1532 mds 1532 g 26 revision 060804 www.idt.com 11.3 ac operating characteristics note 1- v ol must not fall below the level given so that the correct value for iout can be maintained. note 2- measured at 135 mhz, 3.6 vdc, 0 o c, 20 pf, unterminated table 11-3 pin specific i/o ac parameters parameter symbol min. typ. max. units notes ac inputs hsync input frequency f hsync 12 120 khz coast input frequency f pden 30 120 hz analog input (hsync) input high voltage v ih 1.8 5.5 v reg0:7~6 = 00 input low voltage v il vss - 0.3 1.1 v reg0:7~6 = 00 input high voltage v ih 2.3 5.5 v reg0:7~6 = 01 input low voltage v il vss - 0.3 1.1 v reg0:7~6 = 01 input high voltage v ih 1.9 5.5 v reg0:7~6 = 10 input low voltage v il vss - 0.3 1.3 v reg0:7~6 = 10 digital inputs (sda, scl, extfb, osc, i 2 caddr) input high voltage v ih 25.5v input low voltage v il vss - 0.3 0.8 v input hysteresis 0.2 0.6 v por threshold vss 1.8 v voltage that resets register values sda digital output sda output low voltage v ol 0.4 v iout = 3 ma sda output high voltage v oh 6.0 v set by external rset resistor pixel data outputs output impedance r o 65 1 v < v o < 2 v skew from adcrclk tsk 4ns lvcmos outputs (adcrclk, adsync, lock/ref) output impedance r o 45 65 85 1 v < v o < 2 v adcrclk output frequency f s max/2 50 mhz vddd = 3.3 v duty cycle s dc 45 55 % 3
110 mh z t riple 8- bit adc with c lock g enerator mds 1532 g 27 revision 060804 www.idt.com ICS1532 table 11-4 ac operating characteristics (vddx = 3.3 volts, vddx(2.5) = 2.5 volts, temperature = 25 o c parameter symbol min. typ. max. units notes adc resolution 88bits dc accuracy differential nonlinearity dnl +1.2/-1 +2.75/-1 lsb integral nonlinearity inl 2.5 lsb no missing codes by design analog inputs adc input voltage range v ia 0.5 0.7 1.2 vpp input capacitance i c 2pf input resistance i r 1 ? switching performance analog conversion rate 10 110 mhz i2c bus speed 100 4,000 khz vco frequency 150 1,000 mhz sampling clock frequency 10 110 mhz clock jitter 1 ns digital inputs input high voltage v ih 25.5v5.5 input low voltage v il vss-0.3 0.8 v input high current i ih -1 ua input low current i il 1ua input capacitance i c 3pf digital outputs output high voltage v oh vdd-0.1 v output low voltage v ol 0.1 v pixel data output impedance r o 65 1 v < v o < 2 v adcrclk to pixel data skew tsk 5 ns adcrclk duty cycle 45 50 55 % note 2 output coding binary by design power requirements 3.3 v digital supply voltage iddd +3.15 +3.3 +3.45 v 3.3 v analog supply voltage idda +3.15 +3.3 +3.45 v 2.5 v supply voltage idda2.5 +2.35 +2.5 +2.65 v 3.3 v digital supply current 135 ma 110 mhz 3.3 v analog supply current 125 ma 110 mhz 2.5 v supply current 125 ma 110 mhz
110 mh z t riple 8- bit adc with c lock g enerator ICS1532 mds 1532 g 28 revision 060804 www.idt.com total power dissipation 900 1200 mw 110 mhz crystal requirements frequency - parallel resonance 10 14.318 20 mhz load capacitance - 20 - pf zero frequency error by design when the total on-chip + stray capacitance is equal to 20pf. when using spread spectrum functionality, 14.318 mhz is required. dynamic performance analog input bandwidth 450 mhz signal-to-noise ratio snr 32 44 db 108 mhz internal pll crosstalk 50 dbc thermal characteristics junction to case thermal resistance 9 o c/w junction to ambient thermal resistance 32 o c/w flow = 0 m/s table 11-4 ac operating characteristics (vddx = 3.3 volts, vddx(2.5) = 2.5 volts, temperature = 25 o c parameter symbol min. typ. max. units notes
110 mh z t riple 8- bit adc with c lock g enerator mds 1532 g 29 revision 060804 www.idt.com ICS1532 chapter 12 timing diagrams 12.1 ac timing diagrams 12.1.1 phase-locked-loop timing for digital setup and hold the input hsync signal is used to generate the ref output signal. in the phase/frequency detector, the ref signal is compared with adcsync (which provides the recovered hsync signal). table 12-1 gives the timing for these signals, and figure 12-1 shows timing characteristics. figure 12-1. timing for phase-locked loop table 12-1. phase-locked-loop timing time period timing description min typ max units t1 input hsync rise time to ref rise time tbd 7 tbd ns tp adcrclk period ns td adcrclk duty cycle 45-55 50-50 55-45 % t2 adcsync active time 4 x tp ns tp input hsync frequency (reg 03 and 02) + 8 = tp t1 hsync clk adcsync t2 td ref
110 mh z t riple 8- bit adc with c lock g enerator ICS1532 mds 1532 g 30 revision 060804 www.idt.com 12.1.2 digital output data timing figure 12-2. two pixel per clock output data analog in adcrclk pipeline delay = 8 clk p0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 clk p+0 p+1 p-2 p-1 p-4 p-3 p-6 p-5 p-8 p-7 p-10 p-9 p-1 ?a? channel digital data output ?b? channel digital data output p+2 p+3
110 mh z t riple 8- bit adc with c lock g enerator mds 1532 g 31 revision 060804 www.idt.com ICS1532 figure 12-3. ac timing for 2-pixels-per-clock mode table 12-2. timing for 2-pixels-per-clock mode time period timing description min typ max units tp, td clk period, clk duty cycle see table 12-1 .ns t1 clk rise time to adcrclk rise time 2.6 ns t2 acdrclk period t2 = 2 x tp ns t3 digital data skew from adcrclk ns analog data in: ared agrn ablue clk adcrclk ?a? channel digital data output ?b? channel digital data output p1 p0 p+0 tp, td t1 t3 t2 p+1 t3 p2 p3 p4 p5
110 mh z t riple 8- bit adc with c lock g enerator ICS1532 mds 1532 g 32 revision 060804 www.idt.com 12.1.3 adcrclk v.s. adcsync edge relationships and invalid data figure 12-4. adcsync autozero event adcrclk adcsync pixel a data pixel b data valid invalid invalid invalid valid valid valid invalid invalid invalid invalid valid valid invalid invalid invalid valid valid valid invalid invalid invalid invalid valid
110 mh z t riple 8- bit adc with c lock g enerator mds 1532 g 33 revision 060804 www.idt.com ICS1532 12.2 resetting the ICS1532 to a known state below is shown the two ways to re set the ICS1532 to a known state. 12.2.1 reset pin input momentarily bring the active high reset# input pin lo w to cause the part to reset to a known state. 12.2.2 power-on reset (por) timing the ICS1532 incorporates special internal power-on re set circuitry that requires no external reset signal. to use the por circuitry: ? reduce the level of the all supply voltages to the ICS1532 (and the voltage seen on all ICS1532 pins) so that it is below the threshold voltage (vdd th ) of the por circuit for the period t1 shown below ? keep the supply voltage below that threshold vo ltage for time t1, such that power-conditioning capacitors for the printed circuit board are drained and the proper reset state is latched. ? a successful power-on reset results in all the ics153 2 registers having the appropriate reset values as stated in the tables in chapter 4, ?register set? . figure 12-5. power-on reset condition for ICS1532 table 12-3. ICS1532 por transition times symbol timing description min typ max units vdd supply voltage (?on? state) 3.15 3.3 3.45 v vdd th threshold supply voltage 1.8 v t 1 hold time for reset state 10 ms t 1 vdd th vdd min
110 mh z t riple 8- bit adc with c lock g enerator ICS1532 mds 1532 g 34 revision 060804 www.idt.com chapter 13 package dimensions this section gives the physical dimensions for the package for the ICS1532, which is a 144-pin lqfp. ? the lead count (n) for the package is 144 leads. ? the nominal footprint (that is the body) for the package is 20 mm 20 mm 1.4 mm. note: 1. for full mechanical specifications, see jedec drawing number ms-026 rev a. 2. table 13-1 lists the ICS1532 physical dimensions. these dimensions are: a. for planning purposes only. b. subject to change. c. shown in figure 13-1 . table 13-1. physical dimensions for ICS1532 symbol description min. nominal max. unit a full package height 1.60 mm a1 package body standoff (the distance from the seating plane to the base plane of the package body) 0.05 0.15 mm a2 package body thickness 1.35 1.40 1.45 mm b lead width 0.17 0.22 0.27 mm c lead thickness 0.09 0.20 mm d tip-to-tip dimension 22.0 mm d1 package body dimension 20.0 mm e lead pitch 0.50 mm e tip-to-tip dimension 22.0 mm e1 package body dimension 20.0 mm l lead tip length 0.45 0.60 0.75 mm l1 lead length, entire length 1.0 mm q lead tip angle 0 3.5 7 degrees
110 mh z t riple 8- bit adc with c lock g enerator mds 1532 g 35 revision 060804 www.idt.com ICS1532 figure 13-1. physical dimensions for ICS1532 e 1 n d1 d c e e1 top view side view detail view 1 b l1 a a1 a2 seating plane package base plane detail view 2 l
110 mh z t riple 8- bit adc with c lock g enerator ICS1532 mds 1532 g 36 revision 060804 www.idt.com chapter 14 ordering information figure 14-1 ICS1532 ordering information while the information pres ented herein has been chec ked for both accuracy and reliability, integrated device technology, incorpor ated (idt) assumes no resp onsibility for either its us e or for infringement of any patents or other rights of third parties, which woul d result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requir ing extended temper ature range, high reliability, or other extraordinary environmental requirements are not recommended withou t additional processing by idt. idt reserves the right to change any circuitry or sp ecifications without notice. idt doe s not authorize or warrant any idt product for use in life support devices or critical medical instruments. part / order number marking package shipping 1532a ICS1532a 144-pin lqfp trays

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